Xilinx introduces the world's largest capacity FPGA -- Virtex UltraScale+ device

The new Virtex UltraScale+ device will enable the creation of the most complex technologies of the future

Xilinx, Inc. (NASDAQ:XLNX), a global leader in adaptive and intelligent computing, today announced the launch of the world's largest FPGA -- Virtex UltraScale+ VU19P, further extending its 16-nm Virtex® UltraScale+™ product range.With 35 billion transistors, the VU19P has the highest logic density and the largest I/O count ever for a single chip to support simulation and prototype design of the most advanced ASIC and SoC technologies in the future. It will also support a wide range of test measurement, computing, networking, aerospace and defense related applications.

The VU19P sets a new benchmark in the FPGA industry with 9 million system logic units, DDR4 memory bandwidth of up to 1.5 terabits per second, transceiver bandwidth of up to 4.5 terabits per second, and more than 2,000 user I/O.It provides the possibility to create prototypes and simulations of today's most complex SoC, while supporting a variety of complex emerging algorithms such as those used in artificial intelligence (AI), machine learning (ML), video processing, and sensor fusion.The VU19P is 1.6 times larger than the previous generation's industry-maximum-capacity FPGA (the UltraScale 440 FPGA at 20 nm).

"The VU19P not only helps developers accelerate hardware validation, but also enables software integration before ASIC or SoC is available," says Sumit Shah, senior director of product line marketing and management at sarins.VU 19P is the third generation FPGA of cytherins to set the world record.The first virtex-7 2000T, the second Virtex UltraScale VU440, and now the third Virtex UltraScale+ VU19P.The VU19P brings not only cutting-edge chip technology, but also reliable and proven tool flow and IP support."

With a range of debugging tools, visual tools, and IP support, VU19P provides a comprehensive development platform for customers to quickly design and validate new generation applications and technologies.Software/hardware co-validation enables developers to initiate software and custom functionality before acquiring physical devices.In addition, by using the sering Vivado® design suite, you can collaborate to optimize the design process, thereby reducing costs, reducing tablet risk, improving efficiency, and accelerating the product launch process.

Tran Nguyen, ARM's director of design services, said, "ARM relies on therinus devices as the technology to validate our next-generation processor IP and SoC technologies.The new VU19P will support Arm and many other partners in our ecosystem to accelerate the design, development and validation of our most ambitious technology roadmap."

The VU19P will be available in the fall of 2020.